1. Field of the Invention
The present invention relates to a semiconductor device fabrication method, and more particularly to the isolation steps in the fabrication method.
2. Description of the Related Art
The most generally used method of isolating circuit elements in a semiconductor device has been local oxidation of silicon (LOCOS) and a variant of this method known as framed local oxidation of silicon (F-LOCOS). In a further variant, proposed in Japanese Unexamined Patent Application Publication No. 7-22504, oxygen ions are implanted into a silicon substrate to form a buried oxide layer (a pad oxide) while maintaining the monocrystalline structure of the silicon above, and this monocrystalline silicon is then selectively oxidized to form a field oxide with smooth transition or ‘bird's-beak’ regions.
Japanese Unexamined Patent Application Publication No. 6-310534 discloses another method in which an impurity of an opposite type to the source and drain type is implanted into the substrate after the field oxide has been formed. For an n-channel transistor, for example, ions of a p-type impurity such as boron (B+) or boron difluoride (BF2+) may be implanted. This implantation determines the carrier density in the substrate, and thus the threshold voltage of the transistor, and avoids having the carrier density altered by the oxidation process that forms the field oxide. In particular, the impurity concentration near the interface between the active element region and the field oxide can be reliably controlled.
The LOCOS process and its variants do not work well in devices with features as small as, for example 0.15 micrometer (0.15 μm). An alternative process that has come into use at these small geometries is shallow trench isolation (STI), but this process has turned out to be highly problematic when applied to devices having a silicon-on-insulator (SOI) structure, because it stresses the thin silicon layer, greatly degrading the electrical characteristics of the circuit elements formed therein. In particular, STI cannot be used in fully depleted SOI devices in which the silicon layer may be only forty nanometers (40 nm) thick, or less.
For SOI devices, accordingly, alternative isolation methods have been tried, such as the mesa isolation method, in which a thin layer of silicon is etched to form isolated mesas of silicon on an insulating layer. The etching process is illustrated in FIGS. 5A and 5B. An SOI substrate 200 comprising a silicon supporting layer 202, a buried oxide layer 204, and a silicon semiconductor layer 206 is covered with a photoresist film 212 which is patterned by photolithography as shown in FIG. 5A to define the mesa shapes. The silicon semiconductor layer 206 is then etched, with the patterned photoresist functioning as an etching mask. FIG. 5B shows the adjacent parts of two mesas after the photoresist mask has been removed and the surface cleansed. The etching process also removes part of the buried oxide layer 204.
A problem with mesa isolation is that although the silicon semiconductor layer 206 may be thin, its thickness is not so small as to be entirely negligible, and the edges of the mesas are steep. The steep edges create problems in subsequent patterning processes, such as the patterning of gate electrodes by photolithography. In particular, extremely precise photolithography will be required for the formation of gate electrodes with gate lengths of 0.1 μm or less. At these dimensions, the edges of the mesas cannot be ignored, especially since the etching process that forms the mesas increases the height of their edges by etching into the insulating layer 204 as well.